As mentioned, RS485 is used to link devices instead of other means as it provides significant advantages. As mentioned, an example of serial communication is RS485. Here’s an example of a SenseCAP RS485 sensor! Let’s consider a simple example of an RS-485 network with one master device and two slave devices. By adding another 2 wires, making it a 4 wires system, it allows data transmission in both directions to and fro devices at the same time, also known as full-duplex. After a data transfer is initiated by writing to the SPDR data register, the processor may poll the SPSR status register until the SPIF flag is set. Then reading the data that was received (by reading the SPDR) or initiating a new data transfer (by writing to the SPDR) automatically clears the SPIF flag. If SPIF is set, reading the received data or initiating a new data transfer automatically clears the SPIF bit.

The SPIF is set when a data transfer is complete, and is cleared by a read of the SPSR status register, followed by a read or write to the SPDR data register. The MODF bit is cleared by a read of the SPSR followed by a write to the SPCR. WCOL is cleared by a read to the SPSR followed by a read or write to the SPDR. Given a properly wired network and a properly configured SPCR control register, a master device may transmit a message by simply storing the byte to the SPDR data register. If a slave device has already stored a byte into its SPDR register, that byte will be exchanged with the master’s byte. Even though the MOSI pin is not connected to anything, the master initiates a transmission using a "dummy" byte. Although data byte transfers are easily executed once the network has been wired and configured properly, a carefully executed software protocol may be required to ensure data integrity.

The two lowest order bits in the SPCR control register, named SPR1 and SPR0, determine the data exchange frequency expressed in bits per second; this frequency is also known as the baud rate. The next section describes the registers that configure and control the QScreen Controller’s SPI. The QScreen allows the details of the synchronous communications protocol to be customized for compatibility with a variety of peripherals. Setting the MSTR bit initializes the QScreen as a master, and clearing the MSTR bit initializes it as a slave. The interface can be used to support analog to digital and digital to analog converters, networks of many computers controlled by a single master, or networks of devices controlled by several coordinated masters. The flexibility and power of the 68HC11’s serial peripheral interface supports high speed communication between the 68HC11 and other synchronous serial devices. It’s reasonable to question why one wouldn’t simply transmit signals at the quickest possible speed to hasten network updates.The answer lies in the degradation of communication signals due to transmission losses on the cable when the product of the communication trunk length and the baud rate exceeds the recommended limit.

Other elements like wire gauge, biasing circuit characteristics (impedance or capacitance), the existence of stubs from the main trunk, and the physical arrangement of your network cable can all affect your network’s maximum length.Take into account all these factors and maintain a buffer to stay within the advised limit for the overall max network cable length. RS485 main advantages as compared to other serial communication are tolerance to electrical noise, lengthy cable runs, multiple slaves in one connection, and fast data transmission speed. A mode fault occurs when the SPI senses that a multimaster conflict (MC68HC11F1 Technical Data Manual, p.8-7) exists on the network as explained above in connection with the /SS input. Pre-coded device drivers configure the SPI for a standard data format, and it is easy to customize a data format and baud rate for your application. This function properly configures the directions of the SPI I/O pins, and configures the data transfer such that data is valid on the falling trailing edge of the clock, with the clock idling in the low state. If the /SS pin of the master is an input and if a low input level is detected, the processor sets the MODF bit in the SPI status register a "mode fault" condition.

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