If the /SS pin of the master is an output, it can be controlled independently of the SPI system. Disruptions or interference in the differential signal can corrupt data without repetition or reception; a "fire-and-forget" system. The /SS (active-low slave select) signal enables data transfers by slave devices when it is active low. If the /SS input to a slave is active (low), the slave transfers data in response to the SCK clock input that is initiated by the master. The /SS input in turn determines whether the slave responds to the SCK input, as described in a previous section. If the 68HC11 is initialized as a master (by setting the MSTR bit in the SPCR control register as explained below) then bit 5 of the Port D data direction register (DDRD) determines whether /SS is an input or an output. If the 68HC11 is initialized as a master by setting the MSTR bit, then bit 5 of the Port D data direction register (PORTD.DIRECTION) determines whether /SS is an input or an output. Connecting a standard full duplex link RS232 between two computers is the same as with a standard RS232 link, with the TxD (transmitter output) of each computer connected to the RxD (receiver input) of the other computer.

When the communication is complete the slave silences its transmitter so that the master can talk to a different slave on the network. To implement this multi-drop scheme, each slave keeps its RS-232 transmitter silent until it is addressed by the master and is given permission to transmit. To properly operate the network each slave computer executes RS232Silent at startup; thus all of the slave transmitters remain silent individually addressed by the master. The software routines, RS232Transmit() and RS232Silent() control the dual RS232 transmitters on the board. When a slave is addressed, it executes RS232Transmit() at which point full duplex (two-way) communications commences between the master and the selected slave. This allows the processor that is master to control the input /SS pins of other CPU’s, what is rs485 cable for example. The 68HC11 allows the details of the synchronous communications protocol to be customized for compatibility with a variety of peripherals. It provides a convenient means of connecting the QVGA Controller to a variety of peripheral devices, including analog to digital and digital to analog converters, real time clocks, and other computers which use high speed communication.

There are a variety of ways the MOSI, MISO, SCK and /SS pins on your QVGA Controller can be connected. Regardless of the network, however, there are only four signals used: SCK provides a synchronized clock, MOSI and MISO signals are used for data transmission and reception, and /SS configures the 68HC11 as a master or slave device. If the /SS input to a slave is inactive (high), the slave ignores the SCK input, does not transmit or receive data, and keeps its MISO output in a high-impedance state so that it does not interfere with the SPI bus. The /SS pin can be configured as either an input or an output. Initializing the 68HC11 as a slave (by clearing the MSTR bit in the SPCR control register as explained below) automatically configures the /SS pin as an input. Clearing the MSTR bit in the SPCR control register automatically configures the /SS (slave select) pin as an input. Setting the MSTR bit initializes the 68HC11 as a master, and clearing the MSTR bit initializes it as a slave.

Any required SPI output signals must be configured as outputs by setting the appropriate bits in the Port D data direction register which is named PORTD.DIRECTION in the QED-Forth kernel. In this situation, if the /SS input is pulled low while the 68HC11 is the master, the processor detects a "mode fault" (by setting a bit in the SPI status register) meaning that there is more than one master device on the SPI bus. A mode fault occurs when the SPI senses that a multimaster conflict (MC68HC11F1 Technical Data Manual, p.10-5) exists on the network as explained above in connection with the /SS input. It sends data from both directions, following a half-duplex communication mode. It’s reasonable to question why one wouldn’t simply transmit signals at the quickest possible speed to hasten network updates.The answer lies in the degradation of communication signals due to transmission losses on the cable when the product of the communication trunk length and the baud rate exceeds the recommended limit.